The art of electrically isolating semiconductor devices has become an increasingly difficult and important aspect in forming CMOS, DRAM, and SRAM devices including MOSFETS to ensure proper operation. Generally, every FET device must be electrically isolated from other devices to ensure that it operates without electrical interference from other devices. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, consuming a significant amount of power as well as compromising device functionality. Among some examples of reduced functionality include latch-up, noise margin degradation, Voltage threshold shift, cross-talk, and excessive power usage.
Shallow trench isolation (STI) is a preferred electrical isolation technique especially for ultra-large scale integration (ULSI) devices. STI structures allow devices to be placed closer together to achieve a higher level of circuit integration. The STI process generally involves forming trenches in a semiconductor substrate and backfilling with silicon oxide to electrically isolate adjacent active regions for subsequently forming FET devices.
In the STI formation techniques of the prior art, various methods have been proposed for achieving rounded STI trench upper (top) and bottom portions, as rounded corners have been found to decrease electrical field strengths and therefore current leakage. Prior art methods have included various etching strategies including the use of overlying photoresist patterned etching masks to dry etch the STI trench, as well as wet etching methods to form rounded top corners in the STI trench opening following dry etching of the STI trench. As integrated circuit characteristic dimensions continue to be scaled down, it has become increasingly difficult to form STI trench rounded corners with the desired profiles necessary to prevent current leakage. In addition, current leakage at or around STI features is increasingly sensitive to STI trench profiles as devices sizes scale down.
There is therefore a need in the integrated circuit manufacturing art to develop improved methods of forming shallow trench isolation (STI) structures to avoid the problem of undesirable current leakage including improved methods of forming STI trench top and bottom corner portions.
It is an object of the present invention to provide an improved method of forming shallow trench isolation (STI) structures to avoid the problem of undesirable current leakage including improved methods of forming STI trench top and bottom corner portions, in addition to overcoming other shortcomings of the prior art.